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Si Spin Qubits, hergestellt mit modernsten 300-mm-Integrationsverfahren. / Si spin qubits manufactured with state-of-the-art 300mm integration flows.
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  • Electronics (wafers, semiconductors, microchips,...)

The results highlight the maturity of 300mm fab-based qubit processes ultimately enabling large-scale quantum computers.

Imec achieves record-low charge noise for Si MOS quantum dots fabricated on a 300mm CMOS platform

Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, today announced the demonstration of high quality 300mm-Si-based quantum dot spin qubit processing with devices resulting in a statistically relevant, average charge noise of 0.6µeV/√Hz at 1Hz. In view…
The TWINSCAN EXE:5000 High NA EUV scanner in the High NA Lab demonstrating the first-ever 10 nm dense lines obtained in a single exposure.
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  • Electronics (wafers, semiconductors, microchips,...)

Opening of the joint ASML-imec High NA EUV Lithography Lab marks a milestone in preparing High NA EUV lithography for accelerated adoption in mass manufacturing

ASML and imec open joint High NA EUV Lithography Lab offering an early development platform to the leading-edge semiconductor ecosystem

Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, and ASML Holding N.V. (ASML), a leading lithography supplier to the semiconductor industry, today announced the opening of the High NA EUV Lithography Lab in Veldhoven, the Netherlands, a lab jointly run b…
Abbildung 1 - SEM- Querschnittsaufnahme eines Die-to-Wafer hybrid gebondeten Versuchsträgers mit 2µm Bondpadabstand. / Figure 1 – Cross-section SEM image of a die-to-wafer hybrid bonded test vehicle with 2µm bond pad pitch. Abbildung 2 - A) Vision für ein optisch verbundenes Multi-XPU-Rechnersystem auf Waferebene; und B) demonstriertes Testsystem, das aus PIC-Dies mit eingebetteten SiN-Wellenleitern (WG) und evaneszenten Kopplern besteht, die mit einem unteren PIC-Wafer mit komplementären SiN-evaneszenten Kopplern verbunden sind. / Figure 2 – A) Vision for a wafer-level, optically interconnected multi-XPU compute system; and B) demonstrated test system comprising of PIC dies with embedded SiN waveguides (WG) and evanescent couplers bonded to a bottom PIC wafer with complementary SiN evanescent couplers.
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  • Electronics (wafers, semiconductors, microchips,...)

Improved die-to-wafer assembly flow opens doors to logic/memory-on-logic stacking, and to optically interconnected systems-on-wafer

Imec demonstrates die-to-wafer hybrid bonding with a Cu interconnect pad pitch of 2µm

This week, at the 2024 IEEE Electronic Components and Technology Conference (ECTC), imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents a Cu-to-Cu and SiCN-to-SiCN die-to-wafer bonding process resulting in a Cu bond pad pitch of only 2µm at <35…
Abbildung 1. Abbildung des On-Chip-Durchflusszytometers. / Figure 1: Picture of the on-chip flow cytometer. Abbildung 2: (links) Schematischer Querschnitt des Chip-Schichtstapels, der die Lichteinkopplung in den Chip, die Beleuchtung der Zellen sowie die Erfassung und Detektion der Zellstreusignale zeigt. (rechts) Experimentelles Streudiagramm einer vollständigen mononukleären Probe aus peripherem Blut, gemessen mit dem On-Chip-Durchflusszytometer. / Figure 2: (Left) Schematic cross-section of the chip layer stack, indicating light coupling into the chip, cell illumination, and collection and detection of cell scattering signals. (Right) Experimental scatter plot of a full peripheral blood mononuclear sample measured with the on-chip flow cytometer.
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  • Science

On-chip flow cytometer using integrated photonics paves the way for high-throughput cell analysis

Imec and Sarcura introduce scalable on-chip detection of human white blood cells

Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, and Sarcura GmbH, an Austrian early-stage technology start-up, present their proof-of-concept on-chip flow cytometer using integrated photonics. Published on 20th May 2024 in Scientific Reports, part of th…
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  • New building

Spanish government, region of Andalusia and imec sign Memorandum of Understanding (MoU) with the intention to establish a new 300mm R&D process line for specialized chip technologies

New R&D facility will complement imec’s 300mm cleanroom in Leuven with new processes and materials to boost innovation in upcoming domains such as health and augmented and virtual reality.

The Spanish government, together with the regional government of Andalusia and imec, a world-leading research and…
Montage eines High-NA EUV-Tools im gemeinsamen High-NA-Labor von imec und ASML am Hauptsitz von ASML in Veldhoven, Niederlande. (Bildnachweis: ASML) / Assembly of a High NA EUV tool in joint imec-ASML High-NA lab at ASML’s headquarters in Veldhoven, the Netherlands. (Credit: ASML)
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  • Conference

Advances in processes, masks and metrology will enable to fully benefit from the resolution gain offered by the first ASML 0.55NA EUV scanner

Imec demonstrates readiness of the High-NA EUV patterning ecosystem

This week, at the 2024 Advanced Lithography + Patterning Conference, imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, will present the progress made in EUV processes, masks, and metrology prepared for enabling high-numerical aperture (High-NA) extreme ul…
The design pathfinding PDK allows for digital designs with 2nm Gate All Around (GAA) technology including backside connectivity. The design pathfinding PDK allows for digital designs with 2nm Gate All Around (GAA) technology including backside connectivity.
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  • Electronics (wafers, semiconductors, microchips,...)

The design pathfinding PDK lowers the threshold for academia and industry to access the most advanced semiconductor technologies

Imec Launches the First Design Pathfinding Process Design Kit for N2 Node

At the 2024 IEEE International Solid-State Circuits Conference (ISSCC), imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, launches its open process design kit (PDK) with a concomitant training program offered through EUROPRACTICE. The PDK will enable virt…
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  • Electronics (wafers, semiconductors, microchips,...)

ASML is making a substantial commitment in imec's future state-of-the-art pilot line

Imec and ASML sign Memorandum of Understanding (MoU) to support semiconductor research and sustainable innovation in Europe

Imec, a leading research and innovation hub in nanoelectronics and digital technologies, and ASML Holding N.V. (ASML), a leading supplier to the semiconductor industry, today announce that they intend to intensify their collaboration in the next phase of developing a state-of-the-art high-numerical…
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