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All publications from IMEC Belgium

Luc Van de hofe and Nicole Hoffmeister-Kraut
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  • Electronics (wafers, semiconductors, microchips,...)

New partnership enables an innovative network together with academia and industry partners to strengthen digital sovereignty in Europe

Baden-Württemberg attracts imec to lead development of chiplet-based technology for automotive applications

Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, and the State Government of Baden-Württemberg, Germany, today announced, at the Hannover Trade Fair, the launch of the Advanced Chip Design Accelerator (ACDA). The new imec competence center in Baden-Wür…
Abbildung 1 – Top-down-REM-Aufnahmen von Mäandern (links) und Gabeln (rechts) mit 20 nm Abstand nach der Musterübertragung in eine TiN-Hartmaske. / Figure 1 - Top-down SEM pictures of 20nm pitch meanders (left) and forks (right) after pattern transfer into TiN hard mask. Abbildung 2 – TEM-Bild metallisierter Drähte mit 20 nm Abstand nach einem chemisch-mechanischen Poliervorgang (CMP). / Figure 2 - TEM picture of metallized 20nm pitch wires after a chemical mechanical polishing (CMP) step.
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  • Electronics (wafers, semiconductors, microchips,...)

First electrical tests at 20nm pitch present a next milestone in validating the High NA extreme ultraviolet (EUV) patterning ecosystem

Imec demonstrates electrical yield for 20nm pitch metal lines obtained with High NA EUV single patterning

This week at SPIE Advanced Lithography + Patterning, imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents the first electrical test (e-test) results obtained on 20nm pitch metal line structures patterned after single-exposure High NA EUV lithography…
Ein 300 mm Siliziumwafer mit Tausenden von GaAs-Bauelementen mit einer Nahaufnahme mehrerer Dies und eine Rasterelektronenmikroskop-Aufnahme einer Nano-Ridge-Anordnung aus GaAs nach der Epitaxie. / A 300 mm silicon wafer containing thousands of GaAs devices with a close-up of multiple dies and a scanning electron micrograph of a GaAs nano-ridge array after epitaxy. Ein 300 mm Siliziumwafer mit Tausenden von GaAs-Bauelementen mit einer Nahaufnahme mehrerer Dies und eine Rasterelektronenmikroskop-Aufnahme einer Nano-Ridge-Anordnung aus GaAs nach der Epitaxie. / A 300 mm silicon wafer containing thousands of GaAs devices with a close-up of multiple dies and a scanning electron micrograph of a GaAs nano-ridge array after epitaxy.
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  • Electronics (wafers, semiconductors, microchips,...)

Imec achieves breakthrough in silicon photonics, paving the way for cost-effective and high-performance optical devices.

First full wafer-scale fabrication of electrically-pumped GaAs-based nano-ridge lasers on 300 mm silicon wafers

Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, has announced a significant milestone in silicon photonics with the successful demonstration of electrically-driven GaAs-based multi-quantum-well nano-ridge laser diodes fully, monolithically fabricated on…
Abbildung 1 – Konzeptuelle Darstellung (a) eines einreihigen CFET und (b) eines zweireihigen CFET. Das Layout eines Flipflops (D-Flipflop oder DFF) zeigt eine Verringerung der Zellenhöhe und -fläche um 24 nm (oder 12,5 %) beim Übergang von einem einreihigen zu einem zweireihigen CFET (H. Kuekner et al., IEDM 2024). / Figure 1 – Conceptual representation of (a) a single-row CFET and (b) a double-row CFET. The layout of a flip-flop (D-type flip-flop or DFF) shows a reduction of the cell height & area with 24nm (or 12.5%) when transitioning from a single-row to a double-row CFET (H. Kuekner et al., IEDM 2024). Abbildung 2 – Virtueller Prozessablauf für den Aufbau einer zweireihigen CFET-Architektur. Der mit 3D Coventor simulierte Prozessablauf ging von den Spezifikationen einer „virtuellen“ CFET-Fab aus und projizierte zukünftige Verarbeitungskapazitäten und Designspielräume (H. Kuekner et al., IEDM 2024). Die Detailansicht zeigt ein TEM eines monolithischen CFET-Technologie-Demonstrators, der in der 300-mm-Reinraum-F&E-Einrichtung von imec hergestellt wurde (A. Vandooren et al., IEDM 2024). / Figure 2 – Virtual process flow for building a double-row CFET architecture. The process flow, simulated with 3D Coventor, started from the specifications of a ‘virtual’ CFET fab, projecting future processing capabilities and design margins (H. Kuekner et al., IEDM 2024). The zoom-in represents a TEM of a monolithic CFET technology demonstrator fabricated within imec’s 300mm R&D cleanroom facility (A. Vandooren et al., IEDM 2024).
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  • Electronics (wafers, semiconductors, microchips,...)

New standard cell architecture offers the most optimal trade-off between area efficiency and process complexity for logic and SRAM

Imec proposes double-row CFET for the A7 technology node

At the 2024 IEEE International Electron Devices Meeting (IEDM), imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents a new CFET-based standard cell architecture containing two rows of CFETs with a shared signal routing wall in between. The main bene…
Si Spin Qubits, hergestellt mit modernsten 300-mm-Integrationsverfahren. / Si spin qubits manufactured with state-of-the-art 300mm integration flows.
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  • Electronics (wafers, semiconductors, microchips,...)

The results highlight the maturity of 300mm fab-based qubit processes ultimately enabling large-scale quantum computers.

Imec achieves record-low charge noise for Si MOS quantum dots fabricated on a 300mm CMOS platform

Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, today announced the demonstration of high quality 300mm-Si-based quantum dot spin qubit processing with devices resulting in a statistically relevant, average charge noise of 0.6µeV/√Hz at 1Hz. In view…
The TWINSCAN EXE:5000 High NA EUV scanner in the High NA Lab demonstrating the first-ever 10 nm dense lines obtained in a single exposure.
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  • Electronics (wafers, semiconductors, microchips,...)

Opening of the joint ASML-imec High NA EUV Lithography Lab marks a milestone in preparing High NA EUV lithography for accelerated adoption in mass manufacturing

ASML and imec open joint High NA EUV Lithography Lab offering an early development platform to the leading-edge semiconductor ecosystem

Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, and ASML Holding N.V. (ASML), a leading lithography supplier to the semiconductor industry, today announced the opening of the High NA EUV Lithography Lab in Veldhoven, the Netherlands, a lab jointly run b…
Abbildung 1 - SEM- Querschnittsaufnahme eines Die-to-Wafer hybrid gebondeten Versuchsträgers mit 2µm Bondpadabstand. / Figure 1 – Cross-section SEM image of a die-to-wafer hybrid bonded test vehicle with 2µm bond pad pitch. Abbildung 2 - A) Vision für ein optisch verbundenes Multi-XPU-Rechnersystem auf Waferebene; und B) demonstriertes Testsystem, das aus PIC-Dies mit eingebetteten SiN-Wellenleitern (WG) und evaneszenten Kopplern besteht, die mit einem unteren PIC-Wafer mit komplementären SiN-evaneszenten Kopplern verbunden sind. / Figure 2 – A) Vision for a wafer-level, optically interconnected multi-XPU compute system; and B) demonstrated test system comprising of PIC dies with embedded SiN waveguides (WG) and evanescent couplers bonded to a bottom PIC wafer with complementary SiN evanescent couplers.
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  • Electronics (wafers, semiconductors, microchips,...)

Improved die-to-wafer assembly flow opens doors to logic/memory-on-logic stacking, and to optically interconnected systems-on-wafer

Imec demonstrates die-to-wafer hybrid bonding with a Cu interconnect pad pitch of 2µm

This week, at the 2024 IEEE Electronic Components and Technology Conference (ECTC), imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents a Cu-to-Cu and SiCN-to-SiCN die-to-wafer bonding process resulting in a Cu bond pad pitch of only 2µm at <35…
Abbildung 1. Abbildung des On-Chip-Durchflusszytometers. / Figure 1: Picture of the on-chip flow cytometer. Abbildung 2: (links) Schematischer Querschnitt des Chip-Schichtstapels, der die Lichteinkopplung in den Chip, die Beleuchtung der Zellen sowie die Erfassung und Detektion der Zellstreusignale zeigt. (rechts) Experimentelles Streudiagramm einer vollständigen mononukleären Probe aus peripherem Blut, gemessen mit dem On-Chip-Durchflusszytometer. / Figure 2: (Left) Schematic cross-section of the chip layer stack, indicating light coupling into the chip, cell illumination, and collection and detection of cell scattering signals. (Right) Experimental scatter plot of a full peripheral blood mononuclear sample measured with the on-chip flow cytometer.
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  • Science

On-chip flow cytometer using integrated photonics paves the way for high-throughput cell analysis

Imec and Sarcura introduce scalable on-chip detection of human white blood cells

Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, and Sarcura GmbH, an Austrian early-stage technology start-up, present their proof-of-concept on-chip flow cytometer using integrated photonics. Published on 20th May 2024 in Scientific Reports, part of th…
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