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All publications for the rubric Electronics (wafers, semiconductors, microchips,...)

Staatssekretär Dr. Patrick Rapp (r.), Ministerium für Wirtschaft, Arbeit und Tourismus, übergibt der Institutsleitung des Fraunhofer IAF, Dr. Patricie Merkert (m.) und Prof. Dr. Rüdiger Quay (l.), den symbolischen Scheck über die Fördersumme in Höhe von 4,35 Mio. Euro. © Fraunhofer IAF / State Secretary Dr. Patrick Rapp, Ministry of Economic Affairs, Labour and Tourism, hands over the symbolic cheque for the funding amount of 4.35 million euros to the institute management of Fraunhofer IAF, Dr. Patricie Merkert and Prof. Dr. Rüdiger Quay. © Fraunhofer IAF Nach der Scheckübergabe tauscht sich Staatssekretär Dr. Patrick Rapp vor Ort über die APECS-Pilotlinie und die geplanten Aktivitäten des Fraunhofer IAF aus. © Fraunhofer IAF / After handing over the cheque, State Secretary Dr. Patrick Rapp discusses the APECS pilot line and the planned activities of Fraunhofer IAF on site. © Fraunhofer IAF Im Rahmen der APECS-Pilotlinie wird u. a. der Bereich Trockenätztechnik im Reinraum des Fraunhofer IAF für 6‘‘-Wafer erweitert. © Fraunhofer IAF / As part of the APECS pilot line, the area of dry etching technology in the Fraunhofer IAF clean room for 6’’ wafers is being expanded. © Fraunhofer IAF Post-CMOS Druck-sensor-Chiplets mit Wafer-level Gehäu-sen vor ihrer Separierung. © Fraunhofer ISIT / Post-CMOS pressure sensor chiplets with wafer level packaging before dicing. © Fraunhofer ISIT
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  • Know How, Institut

Baden-Württemberg contributes 4.35 million euros in funding as part of the EU Chips Act

Fraunhofer IAF expands technology capabilities for chiplet innovations within the APECS pilot line

Fraunhofer IAF is expanding its technological capabilities in the field of III-V compound semiconductors, making a valuable contribution to the development of the APECS pilot line within the framework of the EU Chips Act. The Baden-Württemberg Ministry of Economic Affairs, Labour and Tourism is con…
Abbildung 1 – Konzeptuelle Darstellung (a) eines einreihigen CFET und (b) eines zweireihigen CFET. Das Layout eines Flipflops (D-Flipflop oder DFF) zeigt eine Verringerung der Zellenhöhe und -fläche um 24 nm (oder 12,5 %) beim Übergang von einem einreihigen zu einem zweireihigen CFET (H. Kuekner et al., IEDM 2024). / Figure 1 – Conceptual representation of (a) a single-row CFET and (b) a double-row CFET. The layout of a flip-flop (D-type flip-flop or DFF) shows a reduction of the cell height & area with 24nm (or 12.5%) when transitioning from a single-row to a double-row CFET (H. Kuekner et al., IEDM 2024). Abbildung 2 – Virtueller Prozessablauf für den Aufbau einer zweireihigen CFET-Architektur. Der mit 3D Coventor simulierte Prozessablauf ging von den Spezifikationen einer „virtuellen“ CFET-Fab aus und projizierte zukünftige Verarbeitungskapazitäten und Designspielräume (H. Kuekner et al., IEDM 2024). Die Detailansicht zeigt ein TEM eines monolithischen CFET-Technologie-Demonstrators, der in der 300-mm-Reinraum-F&E-Einrichtung von imec hergestellt wurde (A. Vandooren et al., IEDM 2024). / Figure 2 – Virtual process flow for building a double-row CFET architecture. The process flow, simulated with 3D Coventor, started from the specifications of a ‘virtual’ CFET fab, projecting future processing capabilities and design margins (H. Kuekner et al., IEDM 2024). The zoom-in represents a TEM of a monolithic CFET technology demonstrator fabricated within imec’s 300mm R&D cleanroom facility (A. Vandooren et al., IEDM 2024).
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  • Electronics (wafers, semiconductors, microchips,...)

New standard cell architecture offers the most optimal trade-off between area efficiency and process complexity for logic and SRAM

Imec proposes double-row CFET for the A7 technology node

At the 2024 IEEE International Electron Devices Meeting (IEDM), imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents a new CFET-based standard cell architecture containing two rows of CFETs with a shared signal routing wall in between. The main bene…
Für Spitzenforschung im Chipdesign entsteht auf dem Campus Süd das KIT Chipdesign House. (Foto: Edelweiss – Fotolia) / The KIT Chipdesign House to be established on KIT’s Campus South will boost cutting-edge chip design research. (Photo: Edelweiss – Fotolia)
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  • Science

Chipdesign House at KIT Founded at KIT – Institution to Accelerate Cutting-edge Chip Design Research in Baden-Württemberg

KIT Chipdesign House to Boost European Chip Production

Be it smartphones, computers, or cars: Nearly all modern technologies are based on powerful microchips. Demand by far exceeds production in Germany. Leading semiconductor manufacturers are mostly based in Asia and North America, from where they supply producers worldwide with their microchips. In or…
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